1. Field of the Invention
The present invention relates to a drive method and circuit for a plasma display panel.
2. Description of the Related Art
Plasma display panels typically offer many features including thin construction, lack of flicker, and high display contrast ratio, and in addition are relatively amenable to large screen applications. They have a high response speed, and in self-emitting types can emit polychromatic light by using a fluorescent. As a result, plasma display panels are becoming increasingly widely used in recent years in the fields of computer-related display devices and color image display devices.
Depending on the method of operation, plasma display panels can be divided between the AC drive type, in which electrodes are covered by a dielectric and alternating-current discharge occurs indirectly, and the DC drive type, in which the electrodes are exposed in a discharge space and direct-current discharge occurs directly. The AC drive type can prevent sputtering of the electrode that is caused by discharge and therefore features longer life. Depending on the drive method for sustaining discharge, this type can be further divided between a paired type in which discharge occurs between confronting opposed electrodes, and a surface discharge type in which discharge occurs between surface discharge electrodes formed on the same substrate.
FIG. 1 presents a sectional view of a display cell constituting an AC-drive surface discharge plasma display panel. This display cell consists of: two insulating substrates 1 and 2 composed of glass, one being the rear surface and the other being the front surface; transparent scan electrode 3 and transparent sustain electrode 4 formed on insulating substrate 1; trace electrodes 5 and 6 layered so as to overlap with scan electrode 3 and sustain electrode 4 and provided for reducing the electrode resistance of scan electrode 3 and sustain electrode 4; dielectric 12 that covers scan electrode 3, sustain electrode 4, and trace electrodes 5 and 6; protective layer 13 composed of a material such as magnesium oxide that is layered on this dielectric 12 to protect dielectric 12 from discharge; data electrode 7 formed on insulating substrate 2 in a direction orthogonal to scan electrode 3 and sustain electrode 4; dielectric 14 that covers data electrode 7; barrier ribs 9 provided on dielectric 14 for both establishing the discharge gas spaces 8 and demarcating display cells; phosphor 11 coated onto dielectric 14 and the side walls of barrier ribs 9 for converting the ultraviolet rays generated by the discharge of discharge gas filing the discharge gas space 8 into visible light 10; and discharge gas space 8 between insulating substrates 1 and 2 that is filled with discharge gas composed of, for example, helium, neon, and xenon or a compound of these gases.
Referring to FIG. 1, explanation is next presented regarding discharge in a selected display cell. When discharge is initiated by the application of a pulse voltage that exceeds the discharge threshold between scan electrode 3 and data electrode 7, a positive or negative charge is drawn to the surfaces of dielectric 12 and 14 on both sides corresponding to the polarity of the pulse voltage to bring about accumulation of charge. The equivalent internal voltage brought about by this accumulation of charge, i.e., the wall potential, is of the reverse polarity of the above-described pulse voltage. As a result, the effective voltage inside the cell decreases as discharge grows, and even if the above-described pulse voltage is maintained at a fixed value, discharge cannot be sustained and eventually comes to an end.
If a sustain pulse, which is a pulse voltage of the same polarity as the wall potential, is subsequently applied between adjacent scan electrode 3 and sustain electrode 4, the wall potential portion combines with this sustain voltage as the effective voltage to exceed the discharge threshold value even if the sustain pulse applied from the outside has a small voltage amplitude, and discharge can therefore be achieved. Discharge can thus be sustained by continuing to apply sustain pulses between scan electrode 3 and sustain electrode 4. This capability constitutes the memory function. In addition, the above-described sustain discharge can be halted by applying to scan electrode 3 or sustain electrode 4 an eraseing pulse, which is a wide and low-voltage pulse that neutralizes the wall potential or a narrow pulse having a voltage on the order of the sustain pulse.
The effective voltage to be applied to a cell remote from the input terminal portion of a large-area display panel is decreased due to the voltage drop across electrode wiring resistance, and this decrease may result in non-uniformity in the emitted luminance within the panel. Since wall potential proportional to the applied voltage is stored in the above-described AC drive, the input terminals of scan electrodes and sustain electrodes that form pairs can be arranged on mutually different panel end portions, whereby the voltage that is effectively applied to a cell can be made substantially uniform in the vertical direction of the panel, thereby allowing prevention of variations in display luminance, which is one cause of loss in panel quality.
FIG. 6 shows an example of the drive waveform applied to each electrode when driving a plasma display having a j.times.k (j, k being natural numbers) dot matrix. Wu is the waveform of the sustain electrode voltage applied in common to sustain electrodes; Ws1, Ws2, . . . , Wsj are the waveforms of scan electrode drive voltage applied to each of a number j of scan electrodes; and Wd is the waveform of the data electrode drive voltage applied to the data electrodes. One drive period consists of priming discharge interval A, writing discharge interval B, and sustain discharge interval C, and a desired image display is obtained by repeating these cycles.
Priming discharge interval A is an interval for generating active particles and wall charge within the discharge gas space so as to obtain stabilized writing discharge characteristics during writing discharge interval B. In priming discharge interval A, priming discharge pulses Pp+ and Pp- are applied to cause all display cells to discharge simultaneously, following which priming discharge eraseing pulse Pe is applied to all scan electrodes simultaneously to erase any charge of the wall charge generated by priming discharge interval A that would hinder writing discharge and sustain discharge. In other words, after first applying priming discharge pulses Pp+ and Pp- to surface discharge electrodes to bring about discharge in all display cells, priming discharge eraseing pulse Pe is applied to scan electrodes to cause erase discharge to erase wall charge that has accumulated due to the priming discharge pulse.
In writing discharge interval B, scan base pulse Pb is first applied to all scan electrodes, following which sequential scan pulse Pw is applied to each scan electrode and a data pulse Pd is selectively applied synchronously with this scan pulse Pw to the data electrodes of display cells that are to display, thereby bringing about writing discharge and generating wall charge in cells that are to display.
Scan base pulse Pb decreases the value of scan voltage Pw, thereby lowering the maximum voltage employed in the drive IC of high withstand voltage that generates scan pulse Pw, and is directed to realizing a low-cost IC. When the value of scan pulse Pw is high, discharge occurs with the rise of scan pulse Pw. This is a harmful discharge that erasees the writing discharge caused by the scan pulse and data pulse. The scan base pulse prevents this harmful discharge by lowering the value of scan pulse Pw.
In sustain discharge interval C, first sustain pulse string Ps1 is applied to sustain electrode and second sustain pulse string Ps2, which has a 180.degree. phase delay with respect to first sustain pulse string Ps1, is applied to each scan electrode, thereby sustaining the necessary sustain discharge to obtain the desired luminance for the display cells in which writing discharge was carried out in writing discharge interval B.
In an AC-drive surface discharge plasma display panel, the surface discharge electrodes made up of scan electrodes and sustain electrodes are both covered with a dielectric, and as a result, the capacitance component is large and the power loss from voltage pulses therefore cannot be ignored. When a sustain voltage pulse of voltage Vs and repetition frequency f is applied between scan and sustain electrodes, the energy P supplied from the power source upon charging or discharging inter-electrode capacitance CP can be represented by equation (1): EQU P=Cp.times.Vs.sup.2 .times.f (1)
This energy P plays no part in gas discharge and is consumed by the resistance of switching elements or panel wiring resistance. Increasing panel size entails not only an increase in the panel capacitance, but an increase in the number of switching elements due to the increase in the gas discharge current, and this is accompanied by an increase in wiring resistance. These factors contribute to both massive power source circuits as well as to display elements having poor energy efficiency due to increase in the total energy consumption.
Plasma display panel drive circuits intended to eliminate ineffectual energy consumption are disclosed in, for example, Japanese Patent Laid-open No. 265397/93 (first example of the prior art) and Japanese Patent Laid-open No. 152865/96 (second example of the prior art).
FIG. 4 is a schematic view of a plasma display panel display device in which the drive circuit of the first example of the prior art is connected to a plasma display panel. Plasma display panel 110 comprises: a plurality of surface discharge electrode pairs made up of scan electrodes and sustain electrodes that are parallel in the horizontal direction and connected in the vertical direction; and a plurality of data electrodes that are parallel in the vertical direction and connected in the horizontal direction and that form pixels at the intersections with the plurality of surface discharge electrode pairs; and includes on opposing panel end portions on the same flat surface the voltage input terminals of the scan electrodes and sustain electrodes that form pairs. Data driver 105 that generates data pulses is connected to plasma display panel 110. The sustain electrodes are connected to sustain driver 101, power recovery circuit 102, and external capacitance 115, and the scan electrodes are connected to sustain driver 108, power recovery circuit 107, and external capacitance 116 by way of scan driver 109.
FIG. 2 is a circuit diagram of the drive circuit of the plasma display device of the first example of the prior art that eliminates ineffectual power consumption. Power recovery circuit 102 consists of coil L201, switches SW201 and SW202, and diodes D201 and D202 for preventing current in the reverse direction; power recovery circuit 107 consists of coil L202, switches SW203 and SW204, and diodes D203 and D204; while sustain drivers 101 and 108 are of push-pull type and consist of two switches SW205 and SW206, and SW207 and SW208, respectively, that connect the power source lines and ground lines.
In the interest of clarifying the power recovery operation during sustain pulse driving, the priming discharge circuit for bringing about generation of stabilized writing discharge and the scan driver have been omitted, and the panel has been simplified as panel capacitance CP201, which is the capacitance between the scan and sustain electrodes.
The power recovery operation when applying sustain voltage pulses of positive polarity to the first example of the prior art is next explained with reference to FIG. 2. Power collecting electrolytic capacitors C201 and C202 are connected in common to one end of power recovery circuit 102 and 107. In this drive circuit, switch SW202 is first turned ON to raise sustain pulses in the sustain interval when switches SW205 and SW206 are OFF and the voltage of the electrodes is 0V, and charge from capacitor C201, which has stored half the voltage of sustain voltage Vs in advance, is supplied by way of diode D202 and coil L201. Coil L201 and panel capacitance CP201 hereupon resonate, the panel electrode potential is raised to close to the level of Vs, and this voltage combined with the wall potential brings about sustained discharge. When the sustain pulse is caused to fall, switches SW202 and SW205 first turn OFF in succession, following which switch SW201 turns ON and charge stored in panel capacitance CP201 passes by way of coil L201 and diode D201 to be collected in capacitor C201. The output potential to the panel drops to close to 0V, whereupon switch S206 turns ON and the potential is decreased all the way to 0V. Switches SW201 and SW206 then turn OFF in succession. The foregoing explanation relates to the recovery operation for the circuit that is connected to coil L201, but the operation of the circuit connected to coil L202 is equivalent with the exception that the repetition period of the sustain voltage pulses is shifted by a half-period.
FIG. 5 is a schematic diagram of a plasma display device in which the circuit of the second example of the prior art is connected to a plasma display. Power recovery circuit 107 in this drive circuit is connected in parallel to panel 110, and external capacitors C201 and C202 of the first example of the prior art are not required.
FIG. 3 shows a plasma display panel drive circuit for a case in which sustain pulses of negative polarity are applied using the second example of the prior art. As in FIG. 2, the scan driver is omitted and the panel capacitance is abbreviated as CP202.
A power recovery circuit comprises: a charging/discharging circuit section including a coil L203 and switches SW211 and SW212 that recharge panel capacitance CP202 to an opposite polarity with the resonant current that is generated when applying sustain pulses, and diodes D205 and D206 for preventing reverse current; and a voltage clamping section for clamping the voltage across panel capacitance CP202 to the power source voltage and to the power source voltage of the opposite polarity and having four switches SW209, SW210, SW213, and SW214 connected between the power source and each end of panel capacitance CP202. Panel capacitance CP202 and the power recovery circuit constitute a resonant circuit. Resonance is caused by the ON and OFF combination of four switches SW209, SW210, SW213, and SW214 when charging/discharging the panel capacitance, and power is recovered by charging the electric charge discharged from the panel in the panel itself.
One problem encountered in the first example of the prior art is that the power collecting capacitors must have sufficient capacitance for the load capacitance, and therefore require time to attain a stabilized state. In addition, driving a large-screen plasma display panel necessitates external capacitors of large capacitance, and this requirement can offset the space saved, which is the chief feature of a flat display. This is because no charge is stored in the capacitors when the power source is powered up and some time is therefore needed before the drive voltage reaches half the voltage that charges the panel capacitance. To quickly obtain stabilized operation, either a separate-system power source must be prepared for supplying in advance from the outside the voltage of half the value for charging the panel capacitance, or a start-up circuit must be provided that can separately supply a kick pulse to the power recovery capacitor. A further disadvantage of this construction is the large number of constituent elements.
The disadvantage of the second example of the prior art is that the power recovery circuit must be provided in parallel with the panel, and connections must be provided between sustain drivers 101 and 108 connected at the two ends of the panel as shown in FIG. 5. The problem in this case lies in the wiring that connects the panel terminals for forming the resonant circuit that is in parallel with the panel capacitance when carrying out recovery. A power recovery circuit can be formed with few components by forming a resonant circuit in parallel with the panel capacitance, but a high peak current flows through the wiring for forming the resonant circuit when charging/discharging and the current path is substantially equal to the panel length. When constructing a large-screen display device, both the electromagnetic wave noise caused by the current flowing through the wiring and the wiring impedance must therefore be taken into consideration, and limitations are also imposed by, for example, the rise of pulses and power loss due to wiring resistance.